The LDT selector and PDBR fields of the TSS give software systems designers flexibility in utilization of segment and page mapping features of the 80386. By appropriate choice of the segment and page mappings for each task, tasks may share address spaces, may have address spaces that are largely distinct from one another, or may have any degree of sharing between these two extremes.
The ability for tasks to have distinct address spaces is an important aspect of 80386 protection. A module in one task cannot interfere with a module in another task if the modules do not have access to the same address spaces. The flexible memory management features of the 80386 allow systems designers to assign areas of shared address space to those modules of different tasks that are designed to cooperate with each other.
The choices for arranging the linear-to-physical mappings of tasks fall into two general classes:
When paging is not enabled, this is the only possibility. Without page tables, all linear addresses map to the same physical addresses.
When paging is enabled, this style of linear-to-physical mapping results from using one page directory for all tasks. The linear space utilized may exceed the physical space available if the operating system also implements page-level virtual memory.
This style is implemented by using a different page directory for each task. Because the PDBR (page directory base register) is loaded from the TSS with each task switch, each task may have a different page directory.
In practice, some portion of the linear address spaces of all tasks must map to the same physical addresses. The task state segments must lie in a common space so that the mapping of TSS addresses does not change while the processor is reading and updating the TSSs during a task switch. The linear space mapped by the GDT should also be mapped to a common physical space; otherwise, the purpose of the GDT is defeated. Figure 7-6 shows how the linear spaces of two tasks can overlap in the physical space by sharing page tables.
By itself, a common linear-to-physical space mapping does not enable sharing of data among tasks. To share data, tasks must also have a common logical-to-linear space mapping; i.e., they must also have access to descriptors that point into a shared linear address space. There are three ways to create common logical-to-physical address-space mappings:
Figure 7-6. Partially-Overlapping Linear Spaces
TSSs PAGE FRAMES +----------+ TASK A TSS PAGE DIRECTORIES PAGE TABLES | TASK A | +----------+ +-----------+ +-----------+ +->| PAGE | | | | | | | | +----------+ | | |-----------| |-----------| | +----------+ | | | | | PTE |--+ | TASK A | | | |-----------| |-----------| +->| PAGE | | | | | | PTE |--+ +----------+ |----------| |-----------| |-----------| +----------+ | PDBR |---->| PDE |---->| PTE |--+ | TASK A | |----------| |-----------| +-----------+ +->| PAGE | | | | PDE |--+ SHARED PT +----------+ +----------+ +-----------+ | +-----------+ +----------+ | | | | SHARED | | |-----------| +->| PAGE | | | | | +----------+ | |-----------| | +----------+ | | PTE |--+ | SHARED | | |-----------| +->| PAGE | |->| PTE |--+ +----------+ TASK B TSS | +-----------+ +----------+ +----------+ +-----------+ | | TASK B | | | | | | +-->| PAGE | | | |-----------| | +-----------+ | +----------+ | | | | | | | | +----------+ | | |-----------| | |-----------| | | TASK B | | | | | | | | | +>| PAGE | |----------| |-----------| | |-----------| | | +----------+ | PDBR |---->| PDE |--+ | PTE |-+ | PAGE FRAMES |----------| |-----------| |-----------| | | | | PDE |---->| PTE |---+ +----------+ +-----------+ +-----------+ TSSs PAGE DIRECTORIES PAGE TABLES