Chapter 5 Memory Management

The 80386 transforms logical addresses (i.e., addresses as viewed by programmers) into physical address (i.e., actual addresses in physical memory) in two steps:

• Segment translation, in which a logical address (consisting of a segment selector and segment offset) are converted to a linear address.
• Page translation, in which a linear address is converted to a physical address. This step is optional, at the discretion of systems-software designers.

These translations are performed in a way that is not visible to applications programmers. Figure 5-1 illustrates the two translations at a high level of abstraction.

Figure 5-1 and the remainder of this chapter present a simplified view of the 80386 addressing mechanism. In reality, the addressing mechanism also includes memory protection features. For the sake of simplicity, however, the subject of protection is taken up in another chapter, Chapter 6.

Figure 5-1. Address Translation Overview

             15           0      31                           0
    LOGICAL +---------------+   +------------------------------+
    ADDRESS |    SELECTOR   |   |            OFFSET            |
            +---------------+   +---+--------------------------+
                                    !
                     +------------------------------+
                     |     SEGMENT TRANSLATION      |
                     +--------------+---------------+
                                 +--+-+       PAGING ENABLED
                                 |PG ?|--------------------+
                                 +--+-+                    |
                   31        PAGING ! DISABLED       0     |
          LINEAR  +-----------+-----------+-----------+    |
          ADDRESS |    DIR    |   PAGE    |  OFFSET   |    |
                  +-----------+-----+-----+-----------+    |
                                    !                      |
                     +------------------------------+      |
                     |       PAGE TRANSLATION       |      |
                     +--------------+---------------+      |
                                    |<---------------------+
                      31            !              0
            PHYSICAL +------------------------------+
            ADDRESS  |                              |
                     +------------------------------+

• 5.1 Segment Translation
• 5.1.1 Descriptors
• 5.1.2 Descriptor Tables
• 5.1.3 Selectors
• 5.1.4 Segment Registers
• 5.2 Page Translation
• 5.2.1 Page Frame
• 5.2.2 Linear Address
• 5.2.3 Page Tables
• 5.2.4 Page-Table Entries
• 5.2.4.1 Page Frame Address
• 5.2.4.2 Present Bit
• 5.2.4.3 Accessed and Dirty Bits
• 5.2.4.4 Read/Write and User/Supervisor Bits
• 5.2.5 Page Translation Cache
• 5.3 Combining Segment and Page Translation
• 5.3.1 "Flat" Architecture
• 5.3.2 Segments Spanning Several Pages
• 5.3.3 Pages Spanning Several Segments
• 5.3.4 Non-Aligned Page and Segment Boundaries
• 5.3.5 Aligned Page and Segment Boundaries
• 5.3.6 Page-Table per Segment
• Figure 5-1. Address Translation Overview
• Figure 5-2. Segment Translation
• Figure 5-3. General Segment-Descriptor Format
• Figure 5-4. Format of Not-Present Descriptor
• Figure 5-5. Descriptor Tables
• Figure 5-6. Format of a Selector
• Figure 5-7. Segment Registers
• Figure 5-8. Format of a Linear Address
• Figure 5-9. Page Translation
• Figure 5-10. Format of a Page Table Entry
• Figure 5-11. Invalid Page Table Entry
• Figure 5-12. 80306 Addressing Machanism
• Figure 5-13. Descriptor per Page Table